Network Interface Buffer Elimination EECS 578 Final Report
نویسندگان
چکیده
Aggressive transistor scaling continues to increase integration capacity with each new technology node. In recent five years, however, the performance gap between Moore’s Law and the art-of-design technology is getting larger, and area and power concerns are drawing much more attention, especially for networkon-chip design. Much attention has been paid on routers, and few on network interface. However, the storage of the data flits in the network interface causes an area overhead and therefore consumes more power. In this project, we propose eliminating buffers in the network interface and preserving the data in the cache instead to reduce overall area. From the simulation result, the proposed design reduces the area of the network interface by 6 times without degrading the performance. Keywords—Network interface, network-on-chip, area saving, buffer elimination
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